
dsPIC30F3014/4013
DS70138G-page 104
2010 Microchip Technology Inc.
FIGURE 16-2:
UART RECEIVER BLOCK DIAGRAM
Read
URX8 UxRXREG Low Byte
Load RSR
UxMODE
Receive Buffer Control
– Generate Flags
– Generate Interrupt
UxRXIF
UxRX
Start bit Detect
Receive Shift Register
16 Divider
Control
Signals
UxSTA
– Shift Data Characters
Read Read
Write
to Buffer
8-9
(UxRSR)
PE
R
FE
R
Parity Check
Stop bit Detect
Shift Clock Generation
Wake Logic
16
Internal Data Bus
1
0
LPBACK
From UxTX
16x Baud Clock from
Baud Rate Generator
or UxARX
if ALTIO = 1